NTT Laboratories uses IPFlexs DAPDNA-2 Dynamically Reconfigurable Processor as the key Device for its Worlds Fastest 10Gbps Firewall

DAPDNA-2 processor enables the next generation in network system security with its dynamic reconfigurability.

December 12 -- IPFlex Inc. (headquartered in Kamiosaki, Shinagawa-ku, Tokyo, president and CEO: Koichi Hagishima, hereafter referred to as IPFlex) today announced that its DAPDNA-2 dynamically reconfigurable processor is used as the key device to enable the worlds fastest packet processing network board, rated at 10Gbps, introduced today by Nippon Telegraph and Telephone Corporation (hereafter referred to as NTT Laboratories).The device is termed Wspeed (see Note 1) by NTT Laboratories.

The board, being able to process high-speed traffic at 10Gbps, makes it possible for the first time to create and test applications for the core network in an environment closely resembling the real world situation. This ability will allow a range of implementations, such as a server interface and a router interface requiring super high-speed packet processing.

The DAPDNA-2 from IPFlex was selected for use on this board because of its high processing capacity in filtering massive quantities of packets, as well as its ability to change and update policy definition without shutting down the network, by making the optimum use of its dynamic reconfiguration characteristics.The DAPDNA-2 processor on this network board reduces access and load on the server, thus making it possible to dramatically reduce total system implementation cost.

In March this year, IPFlex Inc. introduced the DAPDNA-2 (Note 2), a dynamically reconfigurable processor (Note 3) with the unprecedented ability to switch functions by dynamically and instantly changing the circuit configuration within the chip.The processor is for commercial use, suitable for the areas of telecommunications and security where mass capacity high-speed processing is required, and for industrial and medical image data processing. In June this year, IPFlex released the DAPDNA-FW II version 2.3, an integrated development environment for the processor including the facility to generate hardware code directly from the C programming language.

NTT Laboratories adoption of the DAPDNA-2 for the product is significant progress towards the accelerated introduction of the DAPDNA-2 in the field of network system security. This development adds significantly more momentum to the market expansion of dynamically reconfigurable processors, a major strength of IPFlex.

Adoption of the DAPDNA-2 on the 10Gb/s network board
Traditionally, ASICs (Note 4) were used to increase the packet processing speed within the network; however, because of its lack of flexibility, it was necessary to replace the entire hardware when new functions were required.Alternatively, software based approach was also possible but with maximum processing speed of a few hundred Mb/s, the performance was not suitable for core networks.

In addition, security attacks toward networks are ever-evolving.Recent security attacks such as the DDoS attacks (Note 5) and worms (Note 6) have caused massive amount of damage to corporations and individuals worldwide.

In an attempt to solve these problems, NTT Laboratories has been focusing on dynamically reconfigurable processors for the ability to change the hardware circuit easily and flexibly. NTT Laboratories chose IPFlexs DAPDNA-2 as the key device for the product, IPFlex being the world leader in the field of dynamically reconfigurable hardware.

The DAPDNA-2 processor that is built into the board by NTT Laboratories performs at a 10Gb/s wire speed while performing the IPv4 flow identification function.As an example of an application of this product in the network security area, a firewall implementation was tested and proved to be working at the expected level of performance.

10Gb/s Network Board
The network board developed by NTT Laboratories is capable of 10Gb/s wire-speed processing, with an IPv4 flow identification function, and possesses an ability to update the hardware system without disrupting the service. It has become possible for the first time to create an application for the core networks that require processing speed of 10Gb/s-order and at the same time, does not require any downtime.This board can be utilized to develop a range of network applications, such as server interfaces and a router interfaces that require super high-speed packet processing. In addition to the firewall, examples of applying this technology include user policy-based transfer processing on a router, and off-load processing of high-level layer routing and IPSec on high-speed network servers.

About the DAPDNA-2 Dynamically Reconfigurable Processor
On March 17, 2004, IPFlex introduced the DAPDNA-2, the worlds first dynamically reconfigurable processor. This processor is capable of changing its internal configuration instantly, allowing multiple applications, conventionally implemented using multiple chips, to be implemented using a single chip. The DAPDNA-2 is a dual-core processor, comprised of a high-performance RISC processor core, called the DAP, and the DNA, a two-dimensional array of 376 processing elements (PEs). The DAPDNA-2 can be configured to provide the optimal circuitry for a particular application. This configuration takes place not only when the system is initialized, but can also occur dynamically (in a single clock cycle (Note 7) ) while the system is running, to meet the instantaneous needs of the applications implemented by the system.

This unique processor supports high-speed handling of multiple applications in two different ways. With multifunction processing, multiple applications can be called up and executed rapidly. With time-sliced processing, an application can be partitioned into multiple tasks, with one task loading and executing only nanoseconds after the previous task completes.

DAPDNA-FW II version 2.3 Integrated Development Environment
The DAPDNA-FW IIver2.3 Integrated Development Environment is a set of high-performance tools that cover the entire process of developing applications for the DAPDNA processor, from algorithm design through debugging on the actual hardware.

The DAPDNA-FW II version 2.3 environment released on June 7, 2004, supports the following three development methods: Data Flow C Compiler (jointly developed with UK company Celoxica), for direct coding using the C programming language; DNA Designer, which allows drag-and-drop connection of Processing Elements (PEs) for graphical structuring of algorithms; and DNA Blockset, whose high-level language interface allows code creation from The MathWorks MATLAB and Simulink development environments.

Developers of DAPDNA-2-embedded equipment can develop an application using a design method most appropriate to the development environment, and they can meet the market need for a shorter product development cycle and allow products to come to market sooner.

Terminology
(Note 1) Wspeed: Wire-Speed Packet Engine for EDge system
(Note 2) DAPDNA: Digital Application Processor / Distributed Network Architecture
(Note 3) Dynamically Reconfigurable Processor: A processor that is able to dynamically change the circuit configuration within a chip
(Note 4) ASIC: Application Specific Integrated CircuitApplication Specific Integrated Circuit
(Note 5) DDoS Attack: Distributed Denial of Service Attack
Distributed Denial of Service Attach. The attack terminates the service by forcibly sending mass quantities of packets to a targeted computer using several virus-jacked computers.
(Note 6) Worm: An illegal program that self-multiplies via networks
(Note 7) The one clock switching operation is possible by loading the configuration information beforehand in the background

About IPFlex
IPFlex develops dynamically reconfigurable processors and its integrated development software. Dynamically reconfigurable processor based on Digital Application Processor/Distribute Network Architecture (DAPDNA) is designed as a dual-core processor comprised of a high-performance RISC core and a dynamic reconfigurable processor core, and it is a platform that provides hardware performance while maintaining software flexibility. The DAPDNA dynamic reconfigurable processor series is provided with the DAPDNA-FW II as the integrated software development environment. It provides compilers for algorithms written in MATLAB/Simulink and C with data flow extension, thus realizing high-abstraction level algorithm design and leveraging existing intellectual properties of users. Using DAPDNA can dramatically increase programming productivity and cut cost considerably. For more information, please visit : http://www.ipflex.com.

IPFlex, DAPDNA, and Software-to-Silicon are registered trademarks of IPFlex in Japan.

Other company and product names mentioned are trademarks or registered trademarks of the respective companies.

For more information
Miwa Sasaki
Marketing Division
TEL: 03-5436-3861
FAX: 03-5436-3862
E-mail: e-mail protected from spam bots
http://www.ipflex.com

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